The engineer is responsible for the physical design of high density package substrates for Intel GPUs.
The engineer must have a good understanding of flip chip interconnect based leading edge substrate design rules and package assembly driven constraints and rules.
The role requires the engineer to collaborate and work with multiple stakeholders spread across different geos, in a fast-paced environment, from pathfinding phase to the package substrate tape out.Must have experience of at least delivering 2 high density flip chip interconnect based package designs, with engagement from planning/pathfinding phase.
The design engineer must have a strong understanding of the complete Package design flow related to flip chip designs.
The responsibilities include:-Working with Full chip/IP development teams to drive and plan optimal bump patterns, meeting the electrical/performance requirements, substrate and assembly design rules, and cost targets.
This requires to lead the design efforts and develop multiple design options swiftly in a dynamic cross-functional environment during the design cycle.
-Driving the substrate physical design reviews as per plan, and meet the schedule and quality expectations.
-Validating the design using design validation tools.
-Ensuring timely release/tape out of cost optimal high quality package substrates, after reviews with internal stakeholders and with the package substrate manufacturing vendors.
-Identifying areas for improvement - for ex: design tool features, design efficiency, design methods, and proactively seeking to partner with experts/teammates to drive the improvements.
- 2-5 years of experience in the development of competitive Packages for high speed products like CPUs/ASICs/Chipsets/GPUs
.- Strong understanding of package substrate design and package assembly rules.- Must
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