Asic Design Engineer- Camera Isp Design @ Qualcomm

Skills/Experience : Engineer 1 to 3 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains
Experience in Spyglass Lint/CDC checks and waiver creation.
Familiarity with various bus protocols like AHB, AXI
Experience in Bus protocols, NOC ( Network on chip ) is a plus.
Experience in low power design methodology and clock domain crossing designs
Experience in formal verification with Cadence LEC is a plus
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Experience in mobile Multimedia/Camera design is a plus
DSP /ISP knowledge is a plus.
Working knowledge of timing closure is a plus
Expertise in Perl, TCL language
Expertise in post-Si debug is a plus
Good documentation skills
General Should possess good communication skills to ensure effective interaction with Engineering Management and team members.
Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leads across US and Israel
Digital design using Verilog/SV.
Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.
Work in close coordination with Systems, Verification, SoC team , SW team, PD DFT teams to get the goals completed.
Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.

Skills/Experience : Engineer

1 to 3 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains
Experience in Spyglass Lint/CDC checks and waiver creation.

Familiarity with various bus protocols like AHB, AXI

Experience in Bus protocols, NOC ( Network on chip ) is a plus.

Experience in low power design methodology and clock domain crossing designs
Experience in formal verification with Cadence LEC is a plus
Understanding of full RTL to GDS flow to interact with DFT and PD teams

Experience in mobile Multimedia/Camera design is a plus

DSP /ISP knowledge is a plus.

Working knowledge of timing closure is a plus
Expertise in Perl, TCL language
Expertise in post-Si debug is a plus

Good documentation skills

General

Should possess good communication skills to ensure effective interaction with Engineering Management and team members.

Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision

Responsibilities

Digital design and development (RTL) working in close collaboration with Multi-site leads across US and Israel
Digital design using Verilog/SV.

Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.

Work in close coordination with Systems, Verification, SoC team , SW team, PD DFT teams to get the goals completed.
Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.

Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems

Preferred Qualifications

1 years experience with circuit design (e.g., digital, analog, RF). ,1 years experience utilizing schematic capture and circuit simulation software. ,1 years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems