Physical Design Manager
Client: Large Service Company in Semiconductors, part of MNC with revenue of Multi- Billion USD
Location: Bangalore
Proven experience in top level floorplanning/
block partitioning,
Power planning,
understanding and planning of clock mesh structure/
conventional CTS,
Block integration (Including analog IP integration) and
Physical Verification
Signoff. Engineer should have experience in handling chips of GHz clock frequency range &
multi-million instance, and
designed complex chips in lower technology nodes (16nm and below).
Padframe/BGA planning/design,
including RDL routing is required.
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Keyskills: Floor Planning Physical Design clock tree synthesis
Mulya Consulting We are a global, rapidly growing cybersecurity company with over 600 employees across our offices in North America, Europe, Asia Pacific & Latin America. The Director of Engineering in India is a new and pivotal role as you will define the strategic vision for our R&D te...