Lead Dft Engineer - Ahmedabad,Delhi/NCR
- Mulya Consulting
- 7 - 12 years
- Delhi, NCR
- 4 years ago
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Job Description
Client: Large Service Company in Semiconductors, part of MNC with revenue of Multi- Billion USD
Requirement-1
Location: Ahmedabad
8-13 yrs
Hands on experience in various DFT aspects like
Scan insertion,
MBIST
and JTAG,
ATPG,
Pattern validation at block level as well as Fullchip level
- Synopsys tools:
DFT MAX,
TetraMAX
OR Cadence tools:
RTL Compiler,
Encounter Test
OR Mentor Graphics tools:
Tessent tool chain,
TestKompress
- Debussy,
VCS/
Questa
/IUS -
PT tool from Synopsys
Requirement2
Noida
6-11 Years
Incumbent will be responsible for Scan insertion and validation, IP Test, IO Tests, BIST, MBIST insertion and validation, ATPG and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off.
Be responsible for a comprehensive DFT plan and development of the DFT mode timing constraints (SDC)
Incumbent to work with DFT and cross functional teams
To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in SoC/chip
The Lead engineers and coordinate all the DFT activities
Assist to close STA timing across all DFT modes for blocks and top
Responsible for flow-automation
To ensure successful delivery of all the project deliverable to customers
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Job Classification
Industry: Semiconductors, ElectronicsFunctional Area: IT Hardware, Technical Support, Telecom Engineering,
Role Category: IT Hardware
Role: IT Hardware
Employement Type: Full time
Education
Under Graduation: B.Tech/B.E. in Any SpecializationPost Graduation: MS/M.Sc(Science) in Any Specialization, M.Tech in Any Specialization
Doctorate: Doctorate Not Required, Any Doctorate in Any Specialization
Contact Details:
Company: Mulya ConsultingLocation(s): Delhi, NCR
Mulya Consulting
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