Candidate will be responsible for design/developing next generation camera sub systems for mobile phones. Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence.
Skills/Experience Sr Engineer / Sr Lead Engineer
5 to 8 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains
Familiarity with various bus protocols like AHB, AXI
Experience in Bus protocols, NOC ( Network on chip )
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Experience in mobile Multimedia/Camera design is a plus
DSP /ISP knowledge is a plus.
Working knowledge of timing closure is a plus
Expertise in Perl, TCL language
Expertise in post-Si debug is a plus
Good documentation skills
Ability to create unit level test plan
Should possess good communication skills to ensure effective interaction with Engineering Management and team members.
Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision
Digital design and development (RTL) working in close collaboration with Multi-site leads across US and Israel
Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.
Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.
Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.