Advanced understanding of Deep submicron effects and mitigation, Good exposure on Cadence and Mentor Graphics tools. Good understanding of CMOS layouts and process technology in 28nm and below technologies. Hand on experie...

System verilog assertions Perl Functional + Code Coverage Verilog and VHDL Cadence IUS (preferred) or Mentor Questasim Image Sensor knowledge is a plus Experience with SPI / I2C is a plus Qualification: B...

Physical Design Engineer / Sr Engineer / MTS / SMTS : Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power / clock distribution, chip assembly...

DFT Engineers / Sr. Engineer / MTS / SMTS : Specify the DFT Architecture including JTAG functionality, boundary scan, Hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, ...

Layout (Analog / Standardcell) Engineers / Sr. Engineer / MTS / SMTS : Advanced understanding of Deep submicron effects and mitigation, Good exposure on Cadence and Mentor Graphics tools. Good understandin...

ASIC Design Engineers / Sr Engineer / MTS / SMTS ASIC Design Engineers / Sr Engineer / MTS / SMTS : Strong in digital design fundamentals Expertise in micro architecture development, design, RTL Coding ...

Verification Engineers / Sr. Engineer / MTS / SMTS : Expert in UVM / OVM for Verification System verilog assertions Perl Functional + Code Coverage Verilog and VHDL Cadence IUS (preferred) or Mentor Questas...

Job Profile New business development activities through direct sales. Building and maintaining a network of B2B and B2C Clients in the region. Meeting architects and presenting the products Prerequisites Gradu...